1. Field of the Invention
The present invention relates to an improvement of an output buffer of a semiconductor memory and, more particularly, to an output buffer control circuit for controlling a data output timing of the output buffer when data is to be read out from a memory which starts an access operation in response to an address transition detection signal or a chip enable signal.
2. Description of the Related Art
FIG. 1 shows the arrangement of an output buffer control circuit as used in a conventional address access type semiconductor memory such as a CMOS type SRAM (static random access memory), the purpose of the control circuit being to initiate a memory access operation in response to a detection output (ATD signal) from an address transition detector for detecting a transition of an address input. More specifically, a chip enable (CE) signal for controlling the enable/disable state of the memory, an output enable (OE) signal for controlling a data output operation, and a write enable (WE) signal for controlling writing of data in memory cells are input to output control circuit 51, and logical processing is performed. Then, the active/inactive state of output buffer (3-state buffer) 52 is controlled using the resultant logical processing output (output buffer control signal). Note that reference numeral 53 denotes a sense amplifier for detecting/amplifying data from the memory cells and outputting the resultant data to output buffer 52.
FIGS. 2A to 2C show the timing of an address access operation in the above-described memory, wherein the OE signal is rendered active (H level) after an address input transits from A to B while the CE signal is in the enable state (i.e., CE=H level). That is, the OE signal is rendered active after time t1 from when the address transits from A to B, and then output buffer 52 is rendered active after time t2.
Output buffer 52 is in the high impedance state (output open) until it is rendered active. However, if the sum of times t1 and t2 is smaller than a memory access time (a period of time from an address transition until data output from a selected memory cell), output buffer 52 outputs data of a memory cell corresponding to current address B after it outputs data of a memory cell corresponding to preceding address A.
In this case, however, if data from the memory cells respectively corresponding to addresses A and B are different from each other (e.g., memory cell data corresponding to addresses A and B are "0" and "1", respectively), output buffer 52 outputs "0" in the high impedance state, and then outputs the inverted value "1". For this reason, a rapidly changing large current passes through output buffer 52, producing strong noise (output noise and power source noise) in the output signal lines or power source lines (including ground lines) of the memory. In particular when the sum of times t1 and t2 in FIGS. 2A to 2C is close to time t3, data A is output, immediately after which inverted data B is output, producing even greater noise as a result. This noise, is likely to adversely affect for example, the operation of determining the logical level of various input signals to the memory, or the operation of the memory itself or that of a circuit of the back stage commonly connected to a power source with the memory.
FIG. 3 shows the arrangement of an output buffer control circuit as used in a conventional CE access operation type semiconductor memory, this control circuit initiating a memory access operation in response to a CE (chip enable) signal for controlling the enable/disable state of the memory. Referring to FIG. 3, reference numeral 54 denotes a CE buffer; 51, an output control circuit for logically processing an output signal from CE buffer 54, the OE signal, and the WE signal, and outputting an output buffer control signal; and 53, a sense amplifier for detecting/amplifying data from memory cells and outputting the resultant data to output buffer 52.
FIGS. 4A to 4C show the timing of a CE access operation in the above-described memory, wherein an address input transits from A to B, and then the memory is enabled by the CE signal. When the CE signal is enabled (L level), output buffer 52 is rendered active. Then, output data is set in the low impedance state from the high impedance state, and data of a memory cell corresponding to address B is output after access time t.sub.CO.
However, if the OE signal is rendered active (H level) immediately after the CE signal is enabled (L level), or if the OE signal stays at an active state, data of a memory cell corresponding to immediately preceding address A may be output after time t.sub.COE shorter than access time t.sub.CO. In this case, if data of the memory cells respectively corresponding to addresses A and B are different, output buffer 52 outputs "0" level or "L" level in the high impedance state, and then outputs the inverted value, i.e., "1" level or "H" level. For this reason, a current flowing through output buffer 52 is greatly increased, resulting in strong noise (output noise and power source noise) being produced in the output signal lines or power source lines (including ground lines) of the memory. In particular, when time t.sub.COE approaches time t.sub.CO, data A is output, immediately after which inverted data B is output, resulting in even greater noise being produced. Being similar to the noise produced in the circuit of FIG. 1, this noise also adversely affects the operation of determining the logical level of various input signals to the memory, and thus the operation of the memory itself or that of a circuit of the back stage commonly connected to a power source with the memory.
It should be noted that the following reference serves as an example of a conventional technique wherein the above-described problems arise, its contents being incorporated in the description of present invention.
244 1984 IEEE International Solid-State Circuit Conference PA0 ISS C84/Feb. 23, 1984 PA0 SESSION XV: STATIC RAMs PA0 THPM 15.1:
A 46 ns 256K CMOS RAM PA2 Mitsuo Isobe, Junichi Matsunaga, Takayasu Sakurai, Takayuki Ohtani, Kazuhiko Sawada, Hiroshi Nozawa, Tetsuya Iizuka, Susumu Kohyama, PA2 Toshiba Semiconductor Device Engineering Laboratory Kawasaki, Japan